As a solution to limitlessly growing demand on high performance electronic devices, through silicon via (TSV) based 2.5D/3D integrated circuit (IC) has brought a new era of technology evolution. Vertically integrated chips with TSVs as vertical interconnections allow high system bandwidth with maximized number of I/Os, low power consumption with reduced interconnection length, and small form factor by stacking chips in 3-dimension. TSV diameter of less than 10μm and fine pitch fabrication enable thousands of TSVs in each stack of dies for TB/s level of high bandwidth data transmission. Fig. 1 illustrates a conceptual figure of 2.5D/3D IC and SEM image of a TSV applied for vertical integration of memories.

The electrical characteristics of TSVs can be analyzed by equivalent circuit model. As shown in Fig. 2, GSG-type TSV structure is represented as resistance, inductance, conductance, and capacitance (RLGC) lumped circuit components according to the structure and materials. The electrical paths themselves are modeled as series inductance and resistance; the dielectric materials between the conductors or semiconductive silicon substrate are modeled as shunt capacitance and conductance. By analyzing the S-parameter curves, TSVs can be characterized by dominant circuit components in each frequency range.

Fig. 1 A conceptual illustration of TSV based 2.5D/3D IC.

Fig. 2 Equivalent circuit model of GSG-type TSV structure

 

 



 
Recently, the demand on higher performance of electronic products has been increasing continuously. While conventional 2D IC has reached its limits and is insufficient to satisfy the required system bandwidth, interposer-based 2.5D IC and 3D IC have been spotlighted as the solution to realize the improved system bandwidth. Vertical integration of chips on 2.5D and 3D IC has substantially shorter interconnection length and smaller form factor, which allow reduced power consumption and higher bandwidth within a limited area. In 2.5D and 3D ICs, interposer is needed to route high number of signal traces between chip-to-chip and chip-to-package interconnects. Further, to achieve a higher bandwidth within a limited routing area, the data rate of each pin is increasing and metal-to-metal space between the adjacent channels is decreasing. For example, the data rate of the GDDR5, which is implemented in Ultra High Definition Television (UHDTV), is expected to be over 10 Gbps/pin in the near future. Also, to achieve wide I/O and higher bandwidth, the number of pin in a memory is increasing tremendously; especially, High-Bandwidth Memory (HBM) has 1024 I/Os for 1TB channel bandwidth. This large number of I/Os between HBM and GPU are routed on a silicon interposer and fine pitch channels are susceptible to unexpected crosstalk effects. Fig. 1 and Fig. 2 shows the eye-diagram degradation due to the channel degradation effects in the high-speed interposer channel on 2.5D and 3D IC. As the operating frequency of the electronic devices is increasing, not only the crosstalk effects, but also inter-symbol interference (ISI) and channel loss of the substrate degrade the eye-diagram. If the eye-diagram is too much distorted, it could not be able to recover the original transmitted signal at the receiver. Therefore, signal integrity analysis of the high-speed channel is important in pre-manufacturing process.

Fig. 1 Degradation of the eye-diagram due to the Signal Integrity (SI) degradation effects on high-speed and high-bandwidth channel.

Fig. 2 Examples of Signal Integrity (SI) Degradation Effects on high-speed and high-bandwidth channel



 

Today, power integrity (PI) / ground integrity (GI) analysis is essential to ensure reliable performance in high-speed and high-density digital systems. As system requirements have increased, ensuring the system performance has been further challenging with chip, board, and package parasitic components added to the Power Delivery Network (PDN) / Ground Delivery Network (GDN). An example of a PI / GI problem in high-speed and high-density digital systems is simultaneous switching noise (SSN). The PDN / GDN parasitics induce power bounce / ground bounce on the power / ground rails while the number of output drivers of the digital system switch increases at the same time faster. In order to overcome the limitations, 3D IC technology based on TSV has emerged and the emergence of advanced technologies has necessitated analysis on PI / GI of TSV-based 3D ICs.
Our lab quickly recognized the need for PI / GI analysis of 3D-ICs based on TSV, and has been leading this research field globally since the start of research. We are conducting research based on a deep knowledge of PI / GI modeling, simulation and measurement of TSV-based 3D ICs. We go a step further and apply research on high-end commercial products such as HBM. We analyzed HBM's PI / GI and suggested design guidelines for next-generation memory modules along with design guides to improve performance.

 



 
(a) With increasing need for convenience in automotive systems such as unmanned vehicles, the functions of electrical devices are now replacing their mechanical counterparts. Therefore, numerous types of electrical devices in automotive systems have been integrated into automotive systems, e.g., control devices, power devices, and communication devices. We design various analog chips such as analog-to-digital converter (ADC) immune to signal integrity (SI) and power integrity (PI) issues and analyze effects of the magnetic field from a wireless power transfer system a promising technology for automotive charging systems on performance.
(b) These days, portable device with limited battery capacity and server demanding huge amount of energy consumption need high-performance and low-power design. DVFS is a well-known technique to reduce energy in digital systems using off-chip voltage regulators, but the effectiveness of DVFS is hampered by slow voltage transitions. Voltage regulators integrated onto the same chip as the processor core called IVR can provide the benefit of both nanosecond-scale voltage switching and per-core voltage control. Our lab is trying to implement IVR on silicon interposer in active region using CMOS process to take advantage of on-chip IVR and traditional high-efficient off-chip regulator.
(c) Our lab can also design and measure CMOS circuits for wireless power transfer scheme such as various full-bridge rectifiers, LDOs, and DC/DC converters.

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