As total system bandwidth increased, a semiconductor industry has been encountered a memory bandwidth bottleneck toward a high density and high bandwidth system. In order to overcome those limitations, a 3D stacked high bandwidth memory (HBM) based on a through silicon via (TSV) and fine pitch interposer technology is lately introduced. By adopting this structure, thousands numbers of input/output (I/O) channels with a fine pitch can be integrated on HBM interposer which enables a terabyte/s bandwidth system. To establish HBM based interface, it becomes essential to fabricate Silicon interposer due to its capability to process narrow signal width and space. Therefore, Silicon based HBM interposer becomes the key solution to mitigate bandwidth bottleneck of graphics module for high computing system. Since the channels performance are dominantly determined by HBM interposer, the design and analysis of signal and power integrity (SI/PI) for HBM interposer must be preceded thoroughly to guarantee the entire system performance.

Our lab’s advanced package group has focused on electrical design and analysis of silicon interposer for HBM. Based on the material properties and various process constraints, we designed and analyzed memory channels and high speed serial links for the SI optimization of digital system interface. In addition, power distribution network (PDN) analysis for PI optimization was conducted including the effects of through-silicon-via (TSV), RDL via and its PDN. System level hierarchical PDN from main boards to chip was taken into account to evaluate PI issue.


As the amount of data is increasing, memory becomes more important. Dynamic Random Access Memory (DRAM) can proceed the data very fast but it is volatile. NAND Flash Memory can use as huge data storage because of non-volatility. However, NAND Flash proceeds the data relatively slow. To fill the gap between DRAM and NAND Flash Memory, Intel’s 3D X-Point Memory is emerging memory. 3D X-Point Memory released July, 2015 and known as consist of Phase Change Memory (PCM) with Ovonic Threshold Switch (OTS). PCM is a type of new memory that using chalcogenide materials. The chalcogenide material changes between amorphous (high electrical resistivity) and crystalline (low electrical resistivity) state as temperature variation. 3D X-Point Memory is 1000x faster than NAND Flash Memory, 1000x endurance of NAND Flash Memory and 10x denser than DRAM. It’s the breakthrough of memory market, especially high-performance server platform.
Our lab research to the Signal Integrity issues of 3D X-Point memory.(Sneak current issue, Crosstalk and etc.) We are conducting research based on 3D EM simulation model and circuit simulation. We analyze the 3D X-Point memory’s SI and suggest design and simulation for memory applications (SSD, DIMM and etc.) with low latency and high bandwidth.


These days, mobile devices require high integration density both laterally and vertically. System integration based on Fan-out Waver Level Package (FoWLP) provides high integration density both laterally and vertically. FoWLP is based on low-cost organic/glass substrate technology and RDL processes which enable fine line width/space patterning. Figure bellow shows a conceptual view of FoWLP based mobile application processor which includes substrate used to form fan-out region, fine-pitch RDL layers and through FoWLP vias. Also FoWLP has reduced number of metal layers compared to conventional packages and does not require additional package under dies. Due to these reasons, FOWLP technology enables cost-effective and high-density system integration. Compared to 2.5D/3D integration based on TSV and interposer technologies, FoWLP based integration is more cost-effective and at the same time provides compatible integration density compared to 2.5D/3D integration. However, due to reduced number of metal layers, fine line width/space, design becomes challenging. Especially for SoC such as mobile AP which includes many channels and PDNs, design becomes more challenging and may result in SI/PI problems due to tightly routed channels and inductively designed PDNs. Therefore, SI/PI design in FOWLP should be more carefully handled.

Our lab’s advance package group focuses on electrical design and analysis of FoWLP based systems considering SI/PI. Depending on the fabrication processes, different materials are used for fabricating the fan-out region and RDLs. There material properties affect signal integrity of the RDL channels and TMVs. Also ground and power nets design affects signal integrity. We analyze physical and material parameters that affect signal integrity and consider these effects in the design of the FoWLP. When designing power integrity, we not only focuses on FoWLP but also consider chips and system boards hierarchically. We also consider signal/power integrity interactions and design optimal PDN with low power/ground noise.


These days, mobile electrical device technologies require high speed, wide bandwidth, low loss, small size and low cost. However, due to the limit of the Moore’s law, 2-Dimnesional integration technologies are difficult to achieve these requirements. In this respect, 2.5-Dimensional/3-Dimensional integration technologies based on interposers and through vias are essential. In 2.5D/3D integration technologies, silicon is well known materials for substrates of interposers. The silicon interposer has advantages of a fine pitch and matched coefficient of thermal expansion to silicon dies. However, silicon interposers have a high manufacturing cost and loss issues in high frequency ranges over the gigahertz. To overcome these problems, glass substrates are emerging as an alternative solution for silicon substrates. System based on the glass substrate is more cost effective than system based on the silicon substrate. Also, glass substrates have a closely matched coefficient of thermal expansion to silicon dies. Moreover, glass substrates have a merit of the availability of large and thin panel sizes. Furthermore, glass substrates have a low loss property due to a low conductivity of the glass. However, this high resistive, low loss glass substrate generates high PDN impedance peaks at the PDN resonance frequencies. The high PDN impedance peaks disconnect the return current of the through glass via (TGV) channel, increase insertion loss of the channel and induce cross-talk problem. Therefore, SI/PI design in glass interposers should be carefully handled.

Our lab’s advance package group focuses on electrical design and analysis of glass interposers considering SI/PI. To enhance signal performances of the glass interposer, we designed and analyzed channels for the SI optimization considering TGV-TGV noise coupling, channel impedance matching and return current path. Also, modeling and analysis of TGV were conducted. Because TGV is a core technology as an interconnection of the glass interposer. Moreover, to mitigate the PDN resonance of the glass interposer, we proposed the ground shielded-TGV scheme and the electromagnetic band gap structure for the glass interposer.


Today, as smart phones and wearable devices become more common, demand for high-performance and miniaturized semiconductor integrated circuit (IC) is increasing. In this trend, to test package-on-package (PoP) type packages which is arresting attention, a test interposer that provides test access is necessary. Our research group is committed to designing and optimizing test interposers with excellent electrical performance taking account to signal integrity and power integrity; since in order to yield reliable test results, the test equipment should not affect signal and power delivery on the ICs.

Moreover, we collaborate with the socket company for design and optimization for a test socket. Because the test socket interconnects the packaged IC with the motherboard, a poorly designed socket has an adverse effect on the evaluation of the IC due to parasitic components. We are trying to develop the best socket in the world boasting both excellent electrical- and mechanical properties.